In order to facilitate reducing the size and/or power requirements of portable electronic devices such as mobile telephones, personal data assistants and the like, efforts are ongoing to reduce the power consumption of semiconductor memory devices that may be used in such portable electronic devices. One way of reducing the power consumption in dynamic random access memory (DRAM) devices or pseudo SRAMs (also referred to as UTRAMs) is to reduce the amount of current flowing in the device. The overall power consumption of a semiconductor memory device includes both the power dissipated by currents used in the normal operation of the device as well as the power that is dissipated due to leakage currents that result from circuit defects. The leakage currents that may exist in conventional semiconductor memory devices include leakage currents that result from bridges between wordlines and bitlines. Such leakage currents may tend to increase with increasing integration density.
It is known in the art to use redundancy techniques in semiconductor memory devices such as DRAM and UTRAM devices in which spare memory cells are substituted for memory cells that are identified as being permanently defective cells for some reason such as, for example, a determination that the cell has a bridge that is resulting in leakage current. These redundancy techniques may facilitate maintaining a fully operable memory device. However, these redundancy techniques may not shut off the leakage currents that may be generated due to, for example, bridges between bitlines and wordlines.
FIG. 1 shows a core circuit of a memory cell array of a DRAM or UTRAM memory device. The circuit includes a wordline driver circuit 110. As shown in FIG. 1, the wordline driver circuit 110 may be used to activate a selected wordline (e.g., WL0 in FIG. 1) with a boosting voltage VPP in response to a wordline enable signal NWEi, a wordline drive signal PXiD, and a wordline reset signal PXiB. The wordline drive signal PXiD and the wordline reset signal PXiB may be generated from the wordline driver circuit 200 shown in FIG. 2 in response to a main wordline drive signal PXi that is set from a row address signal. The wordline drive signal PXiD actively charges the selected wordline WL0 up to the boosting voltage level VPP, while the wordline reset signal PXiB forces the wordline WL0 to be set to a ground voltage (or other reference voltage) when the wordline is deselected.
A memory cell array block 100 including a plurality of memory cells (exemplary cells 101, 102 are depicted in FIG. 1) may be arranged in rows and columns to form a matrix. The memory cell array block 100 is connected to a bitline equalizer 120 and a bitline sense amplifier (S/A) 130. The bitline equalizer 120 charges a pair of bitlines BL and BLB to a bitline precharge voltage VBL that may, for example, be equal to half of the power supply voltage VDD. The bitline sense amplifier 130 detects and outputs the voltage level of the data stored in a selected memory cell.
A bridge 140 may be formed between the wordline WL0 and the bitline BLB. If this occurs, when the wordline WL0 is not selected, a leakage current path ICC may be formed from the bitline precharge voltage VBL to the reference or ground voltage VSS. As shown in FIG. 1, this leakage current may flow through an equalizing transistor 122, the bitline BLB, the bridge 140, the wordline WL0, and a reset transistor 112 during a refresh operation (and, particularly when the device operates in a self-refresh mode).
FIG. 3 is a timing diagram illustrating operations for driving the wordlines in the semiconductor memory devices of FIGS. 1 and 2 during a self-refresh mode. As shown in FIG. 3, a self-refresh signal PR is set to a high level in response to the rising edge of the first cycle of an address signal that is generated from an internal counter in the self-refresh mode. The activated self-refresh signal PR activates both the main drive signal PXi and the wordline enable signal NWEi to a high level and sets the equalizing signal PEQ to a low level. The activation of the main drive signal PXi activates the wordline drive signal PXiD to a high level and sets the wordline reset signal PXiB to a low level. As shown in FIG. 3, when the counted address signal returns to a low level, the signals PR, PXi, NWEi, PEQ, PXiD, and PXiB are set to a low level, a low level, a low level, a high level, a low level, and a high level, respectively.
As shown in FIG. 1, the transistor 112 is turned on when the wordline reset signal PXiB is set to a high level and the transistor 122 is turned on when the equalizing signal PEQ is set to a high level. The leakage current path ICC from the bitline precharge voltage VBL to the ground voltage VSS travels through the transistor 122, the bitline BLB, the bridge 140, the wordline WL0, and the transistor 112.
The leakage current may flow through cells having a defective bridge structure during the self-refresh mode and/or in a standby mode unless the power supply is shut off. The impact of the leakage current may be more serious in memory chips that are embedded in portable electronic devices because such devices typically have a limited battery life which is further shortened by the leakage currents.